1. Field of the Invention
The present invention relates to epitaxial pinched resistors, and more particularly, to an epitaxial pinched resistor having a smaller conductive cross-sectional area than conventional epitaxial pinched resistors.
2. Description of the Related Art
Epitaxial pinched resistors (also known as "epi FETs" or "bulk pinched resistors") are high value resistors that are often used in bipolar, linear integrated circuits. The textbook entitled "Bipolar and MOS Analog Integrated Circuit Design", by Alan B. Grebene, provides on pages 147-50 an excellent discussion of the structure and operation of epitaxial resistors.
Referring to FIGS. 1A and 1B, an epitaxial pinched resistor 10 includes an n-type epitaxial layer 12 bordered by a p-type isolation diffusion wall 14 over a p-type substrate 28. The epitaxial layer 12 is usually made relatively thick, for example, on the order of 15 micrometers, in order to handle the high voltages applied to the device, which may fall in the range of 25-40 Volts. Ohmic contacts are made to each end of the epitaxial layer 12 with n+-type regions 16, 18, such as required for the emitter of an NPN transistor. A p-type base diffusion region 20, such as is used for the base of an NPN transistor, covers the epitaxial layer 12, except for in the end regions where the n+-type regions 16, 18 are located. The p-type base diffusion region 20 is relatively thin, for example, on the order of 2 micrometers. A layer 26 of SiO.sub.2 covers the n-type epitaxial layer 12, the p-type isolation wall 14, and the p-type base diffusion region 20. Lastly, metal contacts 22, 24 are connected to the n+-type regions 16, 18.
Referring to FIG. 1C, during operation, the width of the n-type epitaxial layer 12 is reduced to the point where the depletion regions extend laterally from the p-type isolation diffusion walls 14 into the epitaxial layer 12. This reduces the conductive, or effective, cross-sectional area of the epitaxial layer 12. Additionally, the p-type base diffusion region 20 further reduces the conductive cross-sectional area and eliminates surface effects. By reducing the conductive cross-sectional area of the epitaxial layer 12, the sheet resistance of that semiconductor region is increased which forms a high-value resistor.
Because the epitaxial layer 12 is surrounded on all sides by the p-type isolation diffusion walls 14, the p-type base diffusion region 20, and the p-type substrate 28, the conductive cross-sectional area of the epitaxial layer 12 is reduced so much that the device eventually pinches off. At around the level of the pinch-off voltage, the device gradually changes from a resistance to a current source. When used as a current source, the epitaxial pinched resistor 10 has been found useful to provide small start-up currents.
As mentioned above, the epitaxial layer 12 is usually made relatively thick, e.g., 15 micrometers. This thickness provides space for the depletion region to spread. However, this thickness also dictates that the p-type isolation diffusion walls 14 be just as thick or deep. During formation of the p-type isolation diffusion walls 14, the isolation diffusion tends to spread laterally as it diffuses vertically. This results in the p-type isolation diffusion walls 14 being very wide near the surface of the chip, thus consuming a large surface area of the chip. It would be desirable to reduce the total surface area of the chip that is consumed by the epitaxial pinched resistor 10.
U.S. Pat. No. 3,901,735 to James L. Dunkley ("Dunkley") entitled "Integrated Circuit Device and Method Utilizing Ion Implanted and Up Diffusion for Isolated Region", discloses an isolation region having two parts. The contents of Dunkley is hereby fully incorporated into the present application by reference. In Dunkley, one region is implanted into the substrate before the epitaxial layer is grown which diffuses upward during subsequent heat cycles, referred to herein as "up isolation". Another region diffuses downward from the top, referred to herein as "down isolation". These two regions meet and surround the epitaxial region. Because the two regions each need to travel a vertical distance which is less than the entire thickness of the epitaxial layer, there is substantially less lateral diffusion of the isolation material than in the scenario where the isolation region needs to travel the entire thickness of the epitaxial layer. This results in an isolation region which requires less surface area of the chip than that shown in FIG. 1B.
FIGS. 2A and 2B show an epitaxial pinched resistor 30 which has been formed using the up-down isolation process described in Dunkley. A first p-type dopant is implanted into the substrate 34 before the epitaxial layer 36 is grown. After the epitaxial layer 36 is grown, a second p-type isolation diffusion region 38 is diffused into the epitaxial layer 36. During a single heat cycle, the first p-type dopant diffuses up creating the isolation diffusion region 32 and the second p-type isolation diffusion region 38 diffuses downward. The isolation regions 32, 38 overlap and isolate a portion of the epitaxial layer 36 which is used for conducting current.
Although the isolation regions 32, 38 shown in FIG. 2A consume less surface area of the chip than the isolation region 14 shown in FIG. 1B, it would nevertheless be desirable to decrease the total consumed surface area of the chip even further. Because there is a need to use epitaxial pinched resistors to provide small start-up currents, and because it is generally advantageous to conserve silicon area, there is a need for an epitaxial pinched resistor which can provide a very small current (on the order of 1 microampere) with a minimum of silicon area, i.e., less surface area than is used by the resistors 10, 30 described above.